1. Field of the Invention
The present invention relates generally to a designing method of a capacitor of a capacitor formed with a MOS transistor. More specifically, the invention relates to a method for optimizing design of a capacitor structure.
2. Description of the Related Art
Upon designing a capacitor employing a MOS transistor, how to set a channel length, a channel width and number of division of a gate electrode is a problem. The problem will be discussed with taking one example of a structure of transistor. FIGS. 5 and 6 are plan view and sections taken along lines b-b' and c-c' of the conventional MOS transistors, in which a case where a channel length L is long, is shown in FIGS. 5, and a case where a channel length L is minimum is shown in FIG. 6.
As shown in FIG. 5, when a channel length L of a capacitor is long, a contact 1A is a contact of a diffusion layer 3A of source or drain of a transistor and a wiring 6A. On the other hand, a contact 1B is a contact of a diffusion layer 3B of source or drain of a transistor and a wiring 6A. These sources or drains are shorted by the wiring 6A via respective diffusion layers 3A and 3B nd contacts 1A and 1B of the wiring 6A. A contact 4A is a contact of a gate electrode 2A of the transistor and a wiring 5A. Channel portions 10 to 12 of a substrate represent center portion and end portions to be channel portions when a potential at the gate electrode 2A exceeds a threshold value of the transistor.
As shown in FIG. 6, when the channel length L of the capacitor is a minimum unit, the contact 1A is a contact of the diffusion layer 3A of the source or drain of the transistor and a wiring 6B. The contact 1B is a contact of the diffusion layer 3B of the source or drain of the transistor and the wiring 6A. Similarly, contacts 1C to 1J are contacts of diffusion layers 3C to 3J of sources and drains of the transistor and the wiring 6A. The sources or drains of the transistor are shorted by the wiring 6A via respective diffusion layers 3A to 3J and the contacts 1A to 1J of the wiring 6A. A contact 4B is a contact of gates 2A to 2H of the transistor and the wiring 5B.
FIG. 7 is an equivalent circuit diagram of the case where the capacitor of FIG. 5 is equally divided into n. A terminal 22 is a gate terminal which corresponds to the wiring 5A of FIG. 5, and a terminal 21 corresponds to the wiring 6A shorting the source and drain. Capacitors C1 to C3 are capacitors of first, second and third gates and channels when the channel is divided into n in the width direction (channel length is also divided into n). Capacitors Cn/2, Cn/2+1, Cn/2+2 are capacitors of (n/2)th, (n/2+1)th and (n/2+2)th gates and channels. Capacitors Cn-1, Cn, Cn+1 are capacitors of (n-1)th, (n)th and (n+1)th gates and channels. Capacitance of the capacitors C1 to Cn+1 become c/(n+1), respectively.
FIGS. 8A to 8C are charts respectively showing voltage levels in the case where the capacitor performs charge/discharge operation at high speed. FIGS. 8A to 8C are variation of internal potential as time goes. In the graphs of FIGS. 8A to 8C, vertical axis represents a potential at respective nodes and horizontal axis represents a distance from the end portion 10 of the diffusion layer on the section b-b' of FIG. 5.
Here, in FIG. 5 (FIG. 7), the initial value of the potential is assumed that the voltage of the gate 2A is the voltages of the diffusion layers 3A and 3B, and the voltages of the wiring 5A and 6A are respective 0V. Here, when the gate 2A (5A) of the transistor is pre-charged to a power source voltage VCC as shown in FIG. 8A, the center portion 11 of the channel of the transistor becomes floating until the gate voltage of the transistor exceeds the threshold value of the transistor. This makes the center portion 11 of the channel in floating in coupling of the gate and channel.
Next, as shown in FIG. 8B, the charge of the center portion 11 of the channel in floating condition is drawn into the grounding level via the gate channels 10 and 12 and the diffusion layers 3A and 3B after the gate voltage of the transistor exceeds the through value of the transistor. At this time, a period required to stabilize the potential at the grounding level becomes 2.2 times of a time contact of the channel from the center portion of the channel to the diffusion layer.
FIG. 9 is a timing chart in the case where charge/discharge operation of the capacitor as illustrated in FIG. 8 is performed at high speed. In a boosting circuit of the MOS transistor for high speed charge/discharge operation of the capacity, due to floating of the center portion 11 of the channel as shown in FIG. 8C, elevating of potential of the diffusion layers 3A and 3B as boosting operation is initiated before the potential becomes stable at the grounding level to reduce voltage variation .DELTA.V of the channel as shown in FIG. 9 to be .DELTA.V'. This makes it impossible to elevate the gate voltage to the desired level after boosting.
Stabilization of floating of the center portion 11 of the channel at the grounding level within a period from starting of pre-charging of the gate of the transistor to initiating elevation of the potential of the diffusion layer, can be achieved by setting the length L of the channel at the minimum unit. However, when the channel length L is set at the minimum unit, the channel width W becomes large correspondingly.
In general, when a capacitor of desired capacity is provided in a capacitor region, division of the capacitor region is performed. Then, number of the regions for the diffusion layers of the capacitor becomes one greater the number of division of the channel width. Therefore, according to increasing of the channel length, number of division of the gate is increased to increase number of the diffusion layer region to make the capacitor region excessively larger.
On the other hand, the desired gate voltage can be attained by setting the capacitance of the capacitor excessively large. However, this inherently cause unnecessary increase of the capacitor region. Furthermore, designing load for certainly providing the capacitor region can be increased. Accordingly, in the conventional designing method, setting of the channel length of the transistor or excessively increase the capacitance without taking the measure as set forth above. However, floating of potential at the center portion 11 of the capacity is inevitable.
As set forth above, the capacitor employing the transistor to be used in the conventional boosting circuit, is elevated the gate potential by elevating the potential of the diffusion layer of the source or the drain after charging the gate of the capacitor. However, after elevating the voltage of the diffusion layer, boosting level of the date can be lower than the boosting potential expected for the boosting circuit to degrade boosting efficiency.
This is because when the gate of the transistor is pre-charged to the power source voltage VCC, the center portion 11 of the channel is held in floating until the gate voltage exceeds the threshold value of the transistor. Since the center portion of the channel is held in floating by coupling of the gate and the channel, the center portion of the channel in the floating condition is drawn to the grounding level via the gate channel and the diffusion layer after the gate voltage exceeds the threshold value of the transistor. However, in the boosting circuit to perform charge/discharge portion of the capacitor at high speed, a period from starting pre-charging of the gate of the transistor to the power source voltage VCC to initiating elevating of potential of the diffusion layer of the source or drain is shorter than the period required to stabilize the center portion of the channel in floating condition at the grounding level. Therefore, as shown in FIG. 9, variation .DELTA.V of the voltage at the channel can be reduced to make it impossible to transfer a sufficient amount of charge to the gate of the transistor. As a result, the gate voltage after boosting cannot reach the expected potential level to reduce voltage variation amount from .DELTA.V to .DELTA.V'.
On the other hand, in the boosting circuit performing charge/discharge operation of the capacitor at high speed, when the capacitor is constructed with a minimum unit of the channel length L, the capacitor region becomes unnecessarily large. Also, designing load therefor is also increased. This result from excessively short channel length in order to stabilize the potential at the center portion in floating state at the grounding level within the period from starting pre-charging of the gate of the transistor to initiation of elevation of the potential of the diffusion layer. This requires greater channel with so as to realize a desired capacity of the capacitor. The region in the width direction of the channel is limited. Therefore, the capacitor is formed by dividing the width of the channel so that the channel may be accommodated in the capacitor region. The diffusion region of the capacitor one greater number than the number of division of the channel width becomes necessary. Therefore, the capacitor region becomes large. Also, for low boosting efficiency, greater capacitance becomes necessary to make the capacitor region excessively large to increase designing load to certainly provide the capacitor region.